The invention relates to a semiconductor device comprising a semiconductor body having a major surface which is adjoined by a comparatively weakly-doped semiconductor region of a first conductivity type, in which the major surface is adjoined by several first zones of a second conductivity type opposite to the first conductivity type which are arranged at regular distances from each other and extend from the major surface down to a smaller depth in the semiconductor body than the semiconductor region. Inside each of these first zones is a comparatively highly-doped second zone of the first conductivity type which is separated in the semiconductor body by the first zone from the semiconductor region, each first zone having a first outer edge and each second zone having a second outer edge, the second outer edge, viewed on the major surface, being located inside the first outer edge and the first and the second outer edge having a substantially equal relative distance substantially throughout their lengths. Each second zone is connected to the adjoining first zone and the first zones are separated at the major surface from each other by a substantially symmetrical grid-shaped part of the semiconductor region which surrounds each of the first zones, this grid-shaped part being covered at the major surface with an insulating layer which extends beyond the first outer edge and at least as far as the second outer edge. On the insulating layer, a conductive layer is present which serves as a gate electrode and covers at least part of the major surface occupied by the grid-shaped part, this conductive layer having openings whose size corresponds to the lateral extent of the first zones located beneath these openings in the semiconductor body.
Such semiconductor devices comprising an insulated gate field effect transistor are known inter alia from British Patent Application GB No. 2087648. In general, the transistor is a power transistor, transistor structures of this kind being also designated as, for example, TRIMOS, HEXFET or SIPMOS. They can be manufactured by means of a technique referred to in the literature as the D-MOS technique.
The first zones generally have the form of a regular polygon and are arranged at equal distances from each other. The semiconductor region constitutes a common drain zone and the second zones constitute source zones, which may be connected to each other by means of a conductive layer. Generally, the second zones have a closed configuration, while the first zone extends as far as the major surface in the central part of the regular polygon and inside the closed configuration of the second zone. The conductive layer, which constitutes the electrical connection of the source zone and hence of the second zone, is then also directly connected to the first zone at the center of the polygon. The first and second outer edges define the actual channel region which adjoins the major surface and in which, at least when the transistor is operated in the conductive condition, a channel controlled by the gate electrode is present between the source zone and the semiconductor region.
It is often desirable that these field effect transistors have a low resistance in the conductive condition. This leads to the use of the described polygonal substructures, in which the goal is a favorable ratio of the channel width to the required semiconductor surface area. Sometimes more complicated topographic forms than the polygons are used. For example, it has already been suggested that the channel region should not follow the complete circumference of a polygon, but that the channel region should be locally bent inwards and then should be returned to the circumference. The channel region then has a meandering form, in which nevertheless the substructure occupies the area of a regular polygon.
For the said series resistance, besides the channel width, the relative distance between the substructures is also of importance. The curent flowing through the transistor has to flow via the intermediate grid-shaped part to the electrical connection of the drain region. This connection may be provided on the side of the semiconductor body located opposite to the major surface if, for example, a single transistor is concerned. Mostly, the comparatively weakly-doped semiconductor region will then be a semiconductor layer which extends on a comparatively highly-doped substrate of the one conductivity type. However, the transistor may also form part of an integrated circuit, in which event the comparatively weakly-doped semiconductor region of the first conductivity type is constituted by an island which at least during operation of the circuit is isolated from the remaining part of the semiconductor body. In this case, the relevant island will be provided with the comparatively highly-doped buried layer of the first conductivity type, and a conducting contact connected to the island may be present at the major surface, for example at the edge of the transistor structure. This conducting contact constitutes, together with the buried layer, the electrical connection of the drain zone. The mutual distance between the substructures influences the spreading resistance in the comparatively weakly-doped semiconductor region, which is met by the current flowing through the transistor between the channel located at the main surface and the highly doped substrate or the highly-doped bured layer. This means in practice that a lower limit is given for the distance between the first outer edges of adjacent first zones.
Besides the serious resistance, the permissible operating voltage is of importance for power transistors. This voltage is mainly determined by the break-down voltage of the pn junctions between the first zones and the adjoining comparatively weakly-doped semiconductor region. In connection herewith it is of importance that these pn junctions are mostly curved in the proximity of the first outer edges of the first zones. It has also to be avoided that the pn junctions can break down at the major surface. It is usual to choose the distance between the second zones so small that the depletion regions of adjacent first zones associated with the pn junctions meet each other before the breakdown voltage is reached. As a result, the equipotential lines will also have a less strongly curved form. Thus, the operating voltage defines an upper limit for the distance between the first outer edges of adjacent first zones.
If the mutual distance between the first zones is chosen so that no breakdown will occur in situ, the breakdown voltage will mostly be determined by the breakdown occurring at the outer edge of the overall pattern of first zones. It is also known from the aforementioned British Patent Application No. 2,087,648 to surround the overall pattern of the first zones by a zone of the second conductivity type having a closed geometry. This zone, which is not provided with an electrical connection, is at a certain distance from the overall pattern of first zones, but is located inside the depletion region associated with the pn junctions of the outer first zones. This floating zone of the second conductivity type serves in known manner inter alia to prevent breakdown at the semiconductor surface. The voltage applied in the reverse direction between the first zones and the semiconductor region is distributed along the major surface between the pn junction limiting the first zone and the pn-junction which forms the outer edge of the floating zone. The floating zone assumes a potential at which the said outer edge is biased in the reverse direction.